.. _program_listing_file_src_sta_HSIOTdmDelay.h:

Program Listing for File HSIOTdmDelay.h
=======================================

|exhale_lsh| :ref:`Return to documentation for file <file_src_sta_HSIOTdmDelay.h>` (``src/sta/HSIOTdmDelay.h``)

.. |exhale_lsh| unicode:: U+021B0 .. UPWARDS ARROW WITH TIP LEFTWARDS

.. code-block:: cpp

   #pragma once
   
   #include <float.h>
   
   #include <map>
   #include <set>
   #include <utility>
   #include <vector>
   
   using std::map;
   using std::pair;
   using std::set;
   using std::vector;
   
   namespace HSFullTiming {
   
   struct PTNet {
     // Net connectivity description.
     // - m_nodes[0] is the source node (driver).
     // - m_nodes[1..] are sinks (receivers); size must be > 1.
     vector<int> m_nodes;
     // Multiplicity for merged nets: one PTNet may represent N identical nets.
     unsigned short m_netNum = 1;
   };
   
   class HSIOTdmDelay {
    public:
     // Manage IO constraints, cut sizes, and compute TDM delay between FPGA pairs.
     HSIOTdmDelay();
   
     // Set a default average cut delay, used when no IO constraint array exists.
     void setAverageCutDelay(float cutDelayAverage);
     // Provide IO constraints and the ratio->delay curves for each constraint
     // array.
     // - ioConnArray: [arrayIndex][fpgaI][fpgaJ] connection counts per IO array.
     // - ratio2delays: [arrayIndex] list of (ratio, delay) pairs, sorted by delay.
     void setIOInfo(const vector<vector<vector<int>>> &ioConnArray,
                    const vector<vector<pair<float, float>>> &ratio2delays);
     // Read back IO constraints and ratio->delay curves currently stored.
     void getIOInfo(vector<vector<vector<int>>> &ioConnArray,
                    vector<vector<pair<float, float>>> &ratio2delays) const;
     // Provide the required cut sizes between FPGA pairs (N x N, symmetric).
     // This triggers internal recomputation in setupTdmCutDelay().
     void setCutSizeArray(const vector<vector<int>> &cutSizeArray);
   
     // True if no IO constraint arrays were provided.
     bool isEmptyIO() const;
   
     // Compute per-pair TDM delays and average delay.
     // If m_netAll is non-empty, uses net-aware routing; otherwise uses aggregate
     // cuts.
     void setupTdmCutDelay();
   
     // Return per-pair TDM delay; falls back to average when matrix is empty.
     float getTdmCutDelay(int fpgaNo1, int fpgaNo2) const;
     // Return average TDM delay across all cuts.
     float getTdmCutDelay() const;
     // Return the full TDM delay matrix.
     const vector<vector<float>> &getTdmCutArray() const;
     // Return routed cut sizes after setupTdmCutDelay().
     // In net-aware flow: routed net usage matrix.
     // In no-net flow: direct pairs stay on edge, routed pairs are expanded to
     // paths. Empty if setupTdmCutDelay() hasn't run or inputs are invalid.
     const vector<vector<int>> &getCutSizeArrayRouting() const;
     // Return remaining channel margin matrix (capacity after cuts/routing).
     const vector<vector<int>> &getChannelMargin() const;
   
     // Debug helpers for printing computed arrays.
     void printTdmArrayInfo() const;
     void printIOInfo() const;
   
     // Sentinel value for "illegal"/unroutable delay.
     float getIllegalDelay() const;
     // True if routing/connection constraints were violated.
     bool isIllegal() const;
     // Group FPGAs into connected components based on legal connectivity.
     set<set<int>> getGroupDatas() const;
   
     // Access the net list; caller may fill m_netAll before setupTdmCutDelay().
     vector<PTNet> &getNetAll();
   
     // Global sentinel used for unreachable delays.
     static float m_defaultDelayMax;
   
    private:
     // Initialize per-channel margins from IO constraints (max available
     // connections).
     void initialChannelMargin();
   
     // Compute delays using explicit net routing when m_netAll is populated.
     void setupTdmCutDelayWithNet();
   
     // Compute delays without net routing. Return pairs that need routing.
     // The return value maps "source FPGA" -> list of destination FPGAs to route.
     map<int, vector<int>> setupTdmCutDelay(vector<vector<int>> &routingCutArray);
   
     // Maximum available connections between two FPGAs across all IO arrays.
     int getMaxConnNum(int fpgaNo1, int fpgaNo2);
     // Compute direct TDM delay given required size, using ratio->delay curves.
     float getDirectTdmDelay(float curSize, int fpgaNo1, int fpgaNo2);
     // Given a delay, interpolate the achievable ratio in a given IO array.
     float getTdmRatio4Delay(float tdmDelay, int arrayIndex) const;
   
     // input data
     // fixed data
     // IO constraints per array (constant after setIOInfo()).
     vector<vector<vector<int>>> m_ioConnArray;
     // Ratio->delay curves per array, sorted by delay ascending.
     vector<vector<pair<float, float>>> m_ratio2delays;  // sort from small to big
     // can update data
     // Required cut sizes between FPGA pairs.
     vector<vector<int>> m_cutSizeArray;
     // Routed cut sizes after applying routing decisions.
     vector<vector<int>> m_cutSizeArrayRouting;
     // Explicit net list (optional); used for net-aware routing.
     vector<PTNet> m_netAll;
     // Total cut size (sum of lower triangle of m_cutSizeArray).
     int m_cutSize = 0;
   
     // tmp data
     // Remaining margin per FPGA pair after allocating cuts.
     vector<vector<int>> m_channelMargin;
     // Total available margin across all pairs.
     int m_marginAll = 0;
   
     // output data
     // Average delay weighted by cut sizes.
     float m_cutDelayAverage = 100;
     // Per-pair TDM delay matrix.
     vector<vector<float>> m_tdmCutDelay;
   
     // Cache of last used connection size for faster interpolation.
     vector<vector<int>> m_curConnectionSize;
   
     // Recompute routing feasibility from cut sizes and IO constraints.
     bool updateDissArray();  // use cutSizeArray, IOArray to update m_dissArray
     // Update delay matrix directly from current routing matrix.
     void updateTdmCutDelayDirectly();
     // Update delay matrix by combining direct delays with routed path delays.
     void updateTdmCutDelayRouting(
         const vector<vector<set<vector<int>>>> &routedPaths);
   
     // True if any pair is unroutable or violates capacity.
     bool m_bIllegal = false;
   };
   
   }  // namespace HSFullTiming